1. Field of the Invention
The present invention relates to the processing of data entries stored in a buffer and associated with objects defined in three-dimensional space to be rendered onto a 2D display, and, more particularly, to the pre-processing of indices used to address the corresponding data entries.
2. Description of the Related Art
Modem multimedia applications place substantial requirements on computing resources. The video gaming industry is of significant commercial value to manufacturers who are constantly striving to develop powerful computing platforms, which provide users with a more exciting interactive experience. The graphics of a video game may be enhanced by creating images that are more life-like. In order for images to be more life-like a video game may require three-dimensional (3D) images and/or the real-time generation of such images. To satisfy these requirements, graphic processors need to perform more operations in a shorter space of time resulting in the need for machines with increased “number-crunching” ability.
The market for “3D” accelerator video cards for PCs and other computing platforms has grown drastically in recent years. It has been recognized that in using a 3D accelerator card, the main central processing unit (CPU) can be freed up by off-loading graphics processing traditionally performed by the CPU. Faster accelerator chips for rendering, or drawing an image allow for more realistic lighting models and higher onscreen polygon counts at higher resolutions.
The technique for rendering a 3D image onto a 2D display involves firstly breaking down the 3D image into polygons defined by primitives. A popular primitive used is a triangle having three vertices. Thus, a 3D image can be transformed into a plurality of triangles each being defined by a unique set of vertices where each vertex would typically contain information relating to co-ordinates (x, y, z), color, texture and lighting. It should be understood that a fairly large storage area is need to accommodate the vertex information. This storage area often referred to as the vertex buffer uses indices to address each of the vertices in the storage area. During the rendering of an image, the graphics processor often has to load and process the same vertex many times thereby replicating the amount of processing carried out.
A 3D card manufacturer, e.g., nVidia, may have a system which uses a transformed vertex cache such that whenever a vertex is required it is first looked up in a cache. If it is already present then the pre-transformed vertex is fetched from the cache. If the vertex is not in the cache, then the vertex is fetched, transformed and stored in the cache. The problem is that this system requires large amounts of cache memory and therefore silicon area. Alternatively, if a smaller cache is chosen only a small number of vertices may be cached and therefore a reasonable number of vertices are still transformed more than once.
Another known method is to pre-transform the whole vertex buffer, save it into main memory and then fetch the transformed vertices as indicated by their indices. The problem with this method is that not all of the vertices may actually be required. In addition, this method requires a large amount of external memory and therefore memory bandwidth.
At least one of the aims of the present embodiment of the invention is to provide a method for reducing vertex processing while still alleviating the aforementioned problems.